The present invention relates the fabrication process of semiconductor devices, and more specifically, to a method for fabricating a P-type metal oxide semiconductor field effect transistor (PMOSFET) with buried source/drain junctions and self-aligned silicide.
From the birth of the first integrated circuit in 1960, the number of devices on a chip has grown at an explosively increasing rate. The progress of the semiconductor integrated circuits has stepped into the ULSI (ultra large scale integration) level or even higher level after almost four decades of development. The capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices, or even billions of devices. Integrated circuit devices like transistors, capacitors, and connections must be greatly narrowed accompanying with this advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within a smaller area without influencing the characteristics and the operations of the integrated circuits. The demands on high packing density, low heat generation, and low power consumption devices with a good reliability and a long operation life must be maintained without any degradation in function. These achievements are expected to be reached with the simultaneous developments and advancements in the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies, namely the big five key aspects of semiconductor manufacturing. The continuous increase in the packing density of the integration circuits must be accompanied by a shrinking minimum feature size. With present semiconductor manufacturing technology, the processes with a generally one-third micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer or even nanometer sizes are highly demanded.
Transistors, or more particularly metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices in the integrated circuits with the high performance. However with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face many risky challenges. As the MOS transistors become narrower and thinner accompanied by shorter channels, problems like the junction punchthrough, the leakage, and the contact resistance, cause the reduction in the yield and reliability of the semiconductor manufacturing processes.
The self-aligned silicidation technology is a vital application to improve the operation speed of the ULSIIVLSI MOS devices in manufacturing the sub-micron feature size semiconductor devices. Unfortunately, there exists some trade-off in employing the technologies like self-aligned silicide. In general, the self-aligned silicidation process results in a high junction leakage coming from the metal penetration. The metal penetration into the silicon substrate spikes the junction and/or the residual metal to cause the leakage problem. The silicide across the LDD spacer, which is not totally removed after the salicidation, causes the bridge between the adjacent devices like the gate and the source/drain regions. The detailed negative effects of the self-aligned silicidation technology on sub-micrometer devices are illustrated in the article by C.Y. Lu et al. (xe2x80x9cProcess Limitation and Device Design Tradeoffs of Self-Aligned TiSi2 Junction Formation in Submicrometer CMOS Devicesxe2x80x9d, in IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991) The device design tradeoffs for a shallow junction with a salicide structure are proposed. Process limitations of both junction formation schemes for sub-micrometer application and future scaling down are also established in the work.
In the present fabrication process, the self-aligned silicide (SALICIDE) technology is widely use to increase the packing density of ULSI circuits and to reduce the interconnect resistance for high speed operation. One of the articles relates to the self-aligned silicide (SALICIDE) technology is the work of K. Fujii et al, titled xe2x80x9cA Thermally Stable Tixe2x80x94W Salicide for Deep-Submicron Logic with Embedded DRAMxe2x80x9d (IEEE, IEDM 96-451, 1996). The above article states that Ti-5%W salicide has high-thermal stability up to 800xc2x0 C. as well as sheet resistance for 0.18 xcexcm devices.
As for xe2x80x9cshort channel effectxe2x80x9d, it could be improved by using the extended ultra-shallow source/drain junction. One of the articles relating to the problems is proposed by A. Hori et al. in their work titled xe2x80x9cA 0.05 xcexcm-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 Kev Ion Implantation and Rapid Thermal Annealingxe2x80x9d (IEEE, IEDM 94-485, 1994). A deep submicron PMOSFET has been fabricated together with a NMOSFET. In the proposed process, ultra shallow source/drain junctions were developed on the basis of 5 KeV ion implantation technology and rapid thermal annealing. The short channel effect was successfully suppressed and the delay time per stage of unloaded CMOS inverter is improved at the supply voltage of 1.5 V.
The proposed method of the present invention forms a P-type metal oxide semiconductor field effect transistor (PMOSFET) with buried source/drain junctions and self-aligned silicide. The application of self-aligned metal silicide source drain contact, in combination with the metal silicide gate contact, raises the operation speed of the transistors. The structure of the extended ultra-shallow source/drain junctions improves the short channel effects in the conventional devices. The packing density of transistors in the integrated circuit can be raised significantly with improved structure formed with the method of the present invention.
The method for fabricating metal oxide semiconductor field effect transistors (MOSFETs) includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A film formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls of the first conductive layer. Doped dielectric sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the doped dielectric sidewall spacers.
Next, the first dielectric layer is removed and a doped silicon layer is selectively deposited on the first conductive layer and on exposed regions of substrate surface. A first metal layer is then formed on the substrate. A thermal process is carried out to to drive in dopants in the doped dielectric sidewall spacers and the doped silicon layer, and to convert portions of the first metal layer into a metal silicide layer lying over the doped silicon layer. The dopants in the doped dielectric sidewall spacers are driven into the substrate to form the extended source/drain junctions, and the dopants in the doped silicon layer are driven into the substrate to form source/drain junctions. A removing step then removes unreacted portions of the first metal layer.
In another preferred embodiment of the present invention, a removing step can be performed, after removing portions of the thermal oxide layer uncovered by the doped dielectric sidewall spacer to remove portions of a substrate surface, in order to form recessed regions on the substrate in regions uncovered by the gate structure and the doped dielectric sidewall spacers, preferably by directly etching a substrate material.
In addition to the aforementioned process of forming MOS transistors, several subsequent steps are typically performed to form interconnections. Firstly, a second dielectric layer is formed on the substrate and an annealing process is performed to the substrate. Portions of the second dielectric layer are removed to form contact holes. A second metal layer is then formed within the contact holes and on the second dielectric layer. Finally, portions of the second metal layer are removed to define interconnections with the remaining metal paths.